The present invention relates to the field of digital computer systems and, more particularly, to a chip having a PCI interface that supports access for both 16- and 32-bit PCI hosts employing little-endian or big-endian byte ordering.
In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus, providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the peripheral component interconnect (PCI) bus. The PCI bus may be a 32-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path that may be attached directly to a system host processor and a memory.
The address and data signals on the PCI bus are time multiplexed on the same 32 pins (ADO through AD31). On the one clock cycle, the combined address/data lines carry the address values and set up the location to move information to or from. On the next cycle, the same lines switch to carrying the actual data.
The PCI bus anticipates all devices following the PCI standard will use its full 32-bit bus width. However, it would be desirable to provide a chip having a PCI interface that allows both 16- and 32-bit host processors to access the chip via a PCI bus.
Further, some processors, such as Intel processors, employ little-endian byte ordering that requires the most significant byte to be in the left-most position. Other processors, such as Motorola processors, use big-endian byte ordering that requires the most significant byte to be in the right-most position.
Moreover, a 16-bit little-endian PCI host drives all address bits ADO to AD31 during the address phase of a PCI transfer, but must transfer data on AD15 to AD0 during the data phase of the transfer. By contrast, a 16-bit big-endian PCI host drives all address bits AD0 to AD31 during the address phase of a transfer, but must transfer data on AD31 to AD16 during the data phase of the transfer.
Thus, it would be desirable to provide a PCI interface that supports little-endian host processors as well as big-endian host processors.
Accordingly, an advantage of the present invention is in providing a chip having a PCI interface that allows both 16- and 32-bit host processors to access internal registers on the chip and an external memory via a PCI bus.
Another advantage of the present invention is in providing a PCI interface that supports little-endian host processors as well as big-endian host processors.
The above and other advantages of the invention are achieved, at least in part, by providing a system for enabling a host to access a memory means via a PCI bus. The memory means may include internal registers of a data communication switch and a memory device external with respect to the switch. Write and read buffers may be arranged on the switch for temporarily storing data transferred between the PCI bus and the memory device. A PCI interface arranged on the switch for transferring data between the PCI bus and the memory means may be adjustable to support a first PCI host that handles words of first length and a second PCI host that handles words of second length different from the first length. For example, the PCI interface may support 16- and 32-bit host processors.
In accordance with a first aspect of the present invention, a data steering means may be provided for connecting predetermined data paths of the PCI bus to a predetermined location of the buffer means in response to a data steering signal. For example, the data steering means allows a 16-bit host to perform an 8- or 16-bit read or write access to the memory device.
In accordance with another aspect of the present invention, a byte swapping means may be provided for changing the order of bytes in a data word when the data word is transferred between the memory device and the buffer. In response to a first byte swapping signal, the order of bytes in the data word may be changed, whereas a second swapping signal may maintain the order of bytes in the data word. For example, the first byte swapping signal may be produced when the switch is configured to support a big-endian host processor. The second byte swapping signal may be generated when the switch is configured to support a little-endian host processor.
In accordance with a further aspect of the present invention, a holding register may be provided between an internal register of the switch and the PCI bus. A plurality of consecutive data transfers may be performed for supporting host accesses to the internal register. The holding register temporarily stores data of a first data transfer and transmits the stored data to the internal register when the host performs a second data transfer directly to the internal register. For example, the holding register may enable a 16-bit host to access a 32-bit internal register using two consecutive 16-bit data transfers.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.